Successive generations of dynamic random access memory components (DRAM) have appeared in the marketplace with steadily shrinking lithographic feature size. As a result, the device storage capacity from each generation has increased. However, it is increasingly becoming more difficult to scale DRAM devices and obtain sufficient capacitive performance for charge storage. DRAM device manufacturing can also be costly.
Various non-volatile memory technologies, such as resistive random access memory (RRAM) and phase change random access memory (PCRAM), to name a few, are relatively inexpensive to manufacture. However, many of the non-volatile memory technologies have yet to attain the performance of their DRAM counterparts. In particular, write operations for such memory technologies often exhibit non-deterministic write times, and undesirable latency characteristics.